Programme
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28 July – 1 August 2014
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Past
1st Day
Day One
09:00 – 10:00
Lecture 1: Introduction: performance evaluation
- Computer organisation revisited
- Hardware/software support for running a program
- Basic techniques in achieving high performance
10:00 – 12:00
Workshop 1: Writing fast code
- Architecture-specific code optimisation
- Performance evaluation
12:00 – 13:00
Poster session 1
13:00 – 14:00
Lunch
14:00 – 15:00
Lecture 2: Parallel programming
- Multicore and computer cluster system
- Data parallelism vs. control parallelism
- Thread based programming
15:00 – 17:00
Workshop 2: Writing parallel code
- POSIX thread programming
- Data parallelism with SSE
2nd Day
Day Two
09:00 – 10:00
Lecture 3: FPGA as a computing device
- Dataflow processing
- Stream processing
- Pipelined architecture
- Interfaces
10:00 – 12:00
Workshop 3: Basic FPGA design flow
- From system specification to bitstream download
12:00 – 13:00
Poster session 2
13:00 – 14:00
Lunch
14:00 – 15:00
Lecture 4: Computer arithmetic & algorithm on FPGAs
- Number representations
- Word width optimisation
- Fast bit operations
- Sorting network
15:00 – 17:00
Workshop 4: Application specific computing units on FPGAs
- Area-power-performance-precision trade off
3rd Day
Day Three
09:00 – 10:00
Lecture 5: High-level synthesis for FPGAs
- High-level languages
- Design environment
10:00 – 12:00
Workshop 5: Programming with high-level synthesis tools
- Leg Up project from University of Toronto
12:00 – 13:00
Poster Session 3
13:00 – 14:00
Lunch
14:00 – 17:00
p.m. Half-day excursion
4th Day
Day Four
09:00 – 10:00
Lecture 6: Domain-specific languages
- General purpose vs domain specific languages
- DSL design flow
10:00 – 12:00
Workshop 6: Programming with hardware construction language
- Chisel high-level language from UC Berkeley
12:00 – 13:00
Poster session 4
13:00 – 14:00
Lunch
14:00 – 15:00
Lecture 7: Hardware-software codesign
- FPGA as an accelerator
- Hardware-software partitioning
- Synchronization and communication
15:00 – 17:00
Workshop 7: Mixed hardware-software execution environment
- HW-SW coprocessing
- Communication and synchronization
5th Day
Day Five
09:00 – 10:00
Lecture 8: GPU as a computing device
10:00 – 12:00
Workshop 8: Programming with GPU
- CUDA programming
12:00 – 13:00
Poster session 5
13:00 – 14:00
Lunch
14:00 – 15:00
Lecture 9: Architectural tradeoffs
- CPU vs FPGA vs GPU
15:00 – 17:00
Workshop 9: One application, three architecture
- Matrix multiply on CPU, FPGA, GPU
17:00 – 17:30
Course wrap-up
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