Ziyi Guan is a PhD student in Electrical and Electronic Engineering at the University of Hong Kong. His research centers on efficient large language models, focusing on quantisation, mixed precision, sparsity, and algorithm-hardware co-design for deployment on constrained platforms. Currently, he is exploring the fusion of formal methods with LLMs to enhance reasoning, with applications in code specification generation, program verification support, and step-wise mathematical problem solving. In addition to methodology, Ziyi builds practical toolchains and collaborates with industry on knowledge-graph-augmented agents. He has presented his work at international conferences in electronic design automation, including prestigious venues such as DAC and ICCAD. Ziyi earned his B.Eng. from SUSTech and has received recognition in competitive technology challenges. His broader interests include systems optimization and trustworthy AI.